1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly, to a nonvolatile memory and a method for fabricating the same.
2. Background of the Related Art
In view of fabrication process, in the nonvolatile memory technology, there are at large the floating gate group and the MIS (Metal-Insulator-Semiconductor) group in which two or three dielectric films are stacked. A related art nonvolatile memory will be explained with reference to the attached drawings. FIG. 1 illustrates a section of a first exemplary related art nonvolatile memory. The nonvolatile memory of the floating gate group shown in FIG. 1 implements memory using a potential well, identical to an ETOX (EPROM with tunnel oxide) widely applied to flash EEPROMs, currently. The nonvolatile memory of the floating gate group employs two or three layered polysilicon process. In the case of three layered polysilicon process, an erasure gate polysilicon layer is provided for use only in erasure exclusively, in which erasure can be controlled, independently. The related art nonvolatile memory shown in FIG. 1 illustrates a nonvolatile memory with two layered polysilicon, provided with a semiconductor substrate 11, a first oxide film 13 formed on the semiconductor substrate 11, a floating gate formed on the first oxide film 13, a second oxide film 17 formed on the floating gate 15, a control gate 19 formed on the second oxide film 17, and source/drain impurity diffusion regions 21 and 21a formed in surfaces of the substrate 11 on both sides of the control gate 19. The first oxide film 13 is called a tunneling oxide film, and the second oxide film 17 is called an IPD (Inter Polysilicon Dielectric).
The programming and erasure operation of the nonvolatile memory of the floating gate group is as follows.
In programming, an adequate positive (+) voltage is applied to the control gate 19, so that the positive voltage couples to the floating gate 15 through the second oxide film 17, an IPD layer, to boost a potential of the floating gate 15. Accordingly, an electric field intensity on the first oxide film 13, a tunneling oxide film, is increased, to cause hot electrons generated by the electric field between the source impurity diffusion region 21 and the drain impurity diffusion region 21a injected into the floating gate 15 through the tunneling oxide film. Eventually, the tunneled electrons in the floating gate 15 is trapped by the tunneling oxide film and the IPD layer, both form a potential well. The erasure is removal of the hot electrons trapped in the potential well from the floating gate 15, in which a negative (-) voltage is applied to the control gate 19 and a positive (+) voltage is applied to the source impurity diffusion region 21, to cause the hot electrons trapped in the floating gate 15 to make a Fowler Nordheim tunneling through the tunneling oxide film into the semiconductor substrate 11.
On the other hand, FIG. 2a illustrates a section of a second exemplary related art nonvolatile memory of the MIS group. The nonvolatile memory of the MIS group implement memory using a trap at an interface of dielectric film-bulk, dielectric film-dielectric film, dielectric film-semiconductor, of which typical one is MONOS/SONOS (Metal-oxide-nitride-oxide-semiconductor/ Polysilicon-oxide-nitride-oxide-semiconductor), that has a simple structure enough to allow application of an existing CMOS fabrication process as it is using single-polysilicon process and an excellent endurance of the programming/erasure.
Referring to FIG. 2a, the nonvolatile memory of the MIS group with an MNOS/SNOS structure is provided with a semiconductor substrate 11, a first oxide film 13 formed on the semiconductor substrate 11, a nitride film 14 formed on the first oxide film 13, a gate electrode 23 on the nitride film 14, and source/drain impurity diffusion regions 21 and 21a formed in surfaces of the semiconductor substrate 11 on both sides of the gate electrode 23. In order to content a scale-down, the foregoing nonvolatile memory of the MIS group with an MNOS/SNOS structure should have a thickness of the nitride film 14 reduced. However, as already reported, the thickness of the nitride film 14 can not be reduced below 180 .ANG. which is two times of 90 .ANG., a center of electrons, in view that the center of electrons are 90 .ANG. in the nitride film 14. An art developed to overcome the scale-down limit of the MNOS/SNOS structure is the MONOS/SONOS structure. That is, as shown in FIG. 2b, the MONOS/SONOS structure is provided with a semiconductor substrate 11, a first oxide film 13 formed on the semiconductor substrate 11, a nitride film 14 formed on the first oxide film 13, a second oxide film 17 formed on the nitride film 14, and a gate electrode 23 formed on the second oxide film 17. As shown in the drawing, an O--N--O structured dielectric film is provided between the gate electrode 23 and the semiconductor substrate 11.
The programming and erasure operation of the nonvolatile memory of MONOS/SONOS structure will be explained.
In programming, an adequate positive (+) voltage is applied to the gate electrode 23, so that electrons are injected from the semiconductor substrate 11 to the nitride film 14 passing through the first oxide film 13 on the semiconductor substrate 11 by tunneling. In this instance, the second oxide film 17 on the nitride film 14 blocks both leakage of the electrons injected to the nitride film 14 toward the gate electrode 23 and injection of holes from the gate electrode 23 into the nitride film 14. In this sense, the first oxide film 13 is called as a tunneling oxide and the second oxide film 17 on the nitride film 14 is called as a blocking oxide film. The electrons injected through the first oxide film 13, the tunneling oxide film, are trapped in a nitride film 14 bulk trap and interface traps at both ends of the nitride film 14, with an increased threshold voltage. Therefore, in order to erase, a negative (-) voltage is applied to the gate electrode 23, so that the trapped electrons are discharged to the semiconductor substrate 11, dropping the threshold voltage to a value before programming. The merits of the foregoing nonvolatile memory of MONOS/SONOS structure comes from the blocking oxide film having a function of a potential barrier. That is, even if a thickness of the nitride film is reduced, the blocking oxide film blocks leakage of the electrons injected into the nitride film 14 and has a comparatively large memory window owing to a high concentration trap formed at an interface of the nitride film-the blocking oxide film. The memory window is a difference of threshold voltages between programming and erasure. And, the blocking oxide film blocks injection of holes from the gate electrode 23, that degrades a device performance, the nonvolatile memory of MONOS/SONOS structure has a high reliability.
However, the related art nonvolatile memories have the following problems.
First, use of the two-, or three layered polysilicon in the nonvolatile memory of floating gate group results in a great step as high as 5000 .ANG. and over, which causes a complicated fabrication process.
Second, despite of the foregoing merits of the nonvolatile memory of MIS group, the nonvolatile memory of MIS group essentially requires growth of an ultra-thin tunneling oxide film of below 20 .ANG. for having a low programming voltage and fast programming. However, the growth of an ultra-thin tunneling oxide film with assured reproducibility and reliability requires a very difficult and sophisticated fabrication process. That is, either a high temperature, and ultra high vacuum cleaning process should be conducted before the oxide film growth or a separate furnace for conducing a silicon oxide film growth and a silicon nitride film deposition on the same time is required for preventing growth of a natural oxide film.